Method of decoding low density parity check (ldpc) code, decoder and system performing the same

A low density parity check (LDPC) decoder that divides a parity check matrix of an LDPC code, into a plurality of sub blocks and performs a decoding operation for each of a plurality of decoding iterations, the LDPC decoder comprising:

• a variable node processor and a check node processor configured to perform a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule;
• a reliability estimator configured to estimate a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks;
• and
• an update manager configured to adjust the decoding schedule, based on the reliability of each of the target sub blocks.

A memory system comprising:

• a memory device comprising a plurality of memory cells;
• a memory controller configured to control an operation of the memory device;
• and
• a low density parity check (LDPC) decoder configured to:
• divide a parity check matrix of an LDPC code that is read from the memory cells, into a plurality of sub blocks;
• and
• perform a decoding operation for each of a plurality of decoding iterations, wherein the LDPC decoder comprises:
• a variable node processor and a check node processor configured to perform a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule;
• a reliability estimator configured to estimate a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks;
• and
• an update manager configured to adjust the decoding schedule, based on the reliability of each of the target sub blocks.