Interleaving quantizer in continuous-time delta-sigma modulator for quantization level increment

A continuous-time delta-sigma modulator, comprising:

• a receiving circuit, for receiving an input signal and a feedback signal to generate a first signal;
• a loop filter, for filtering the first signal to generate a filtered signal;
• a first analog-to-digital converter (ADC), for sampling the filtered signal to generate a first digital signal;
• a second ADC, for sampling upon the filtered signal to generate a second digital signal;
• a combiner, for combining the first digital signal and the second digital signal to generate an output signal of the continuous-time delta-sigma modulator;
• and
• a feedback circuit, coupled to the first ADC and the second ADC, for generating at least one feedback signal according to the first digital signal and the second digital signal;
• a first switch coupled between an output node of the loop filter and the first ADC;
• a second switch coupled between the output node of the loop filter and the second ADC;
• wherein the first ADC and the second ADC sample the filtered signal at different times, and the first digital signal generated by the first ADC and the second digital signal generated by the second ADC are provided to the feedback circuit;
• wherein the first switch is controlled by a first clock signal, and the second switch is controlled by a second clock signal whose phase is different from a phase of the first clock signal, to make the first ADC and the second ADC sample the filtered signal at different times.

A continuous-time delta-sigma modulator, comprising:

• a receiving circuit, for receiving an input signal and a feedback signal to generate a first signal;
• a loop filter, for filtering the first signal to generate a filtered signal;
• a analog-to-digital converter (ADC), for sampling the filtered signal to generate a first digital signal, and sampling the filtered signal to generate a second digital signal at different times;
• a combiner, for combining the first digital signal and the second digital signal to generate an output signal of the continuous-time delta-sigma modulator;
• and
• a feedback circuit, coupled to the ADC, for generating at least one feedback signal according to the first digital signal and the second digital signal.
• a first switch coupled between an output node of the loop filter and the ADC;
• a second switch coupled between the output node of the loop filter and the ADC;
• wherein the first switch is controlled by a first clock signal, and the second switch is controlled by a second clock signal whose phase is different from a phase of the first clock signal, to make the ADC samples the filtered signal to generate the first digital signal and the ADC samples the filtered signal to generate the second digital signal at different times.