Frequency management for interference reduction of a/d converters powered by switching power converters

A system, comprising:

• a phase-locked loop (PLL) configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency;
• a power converter configured to produce a power signal that corresponds at least in part to the second frequency;
• a clock transmitter configured to transmit the first clock signal through a first electrical isolation barrier;
• a clock receiver configured to receive the first clock signal from the clock transmitter;
• an analog-to-digital converter (ADC) configured to receive the first clock signal from the clock receiver and to sample and convert electrical measurements at the first frequency, the ADC powered by the power signal;
• a data transmitter configured to receive an output of the ADC and to transmit the output of the ADC via a second electrical isolation barrier;
• and
• a data receiver configured to receive the output of the ADC from the data transmitter and to direct the received output of the ADC toward a device pin,
• wherein the second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from at least one harmonic frequency of the first frequency.

A method, comprising:

• using a frequency generator to generate a second clock signal at a second frequency based on a first clock signal at a first frequency, the first and second frequencies offset from each other by target margins;
• generating a power signal having a direct current (DC) component and an alternating current (AC) component, the AC component corresponding to the second frequency;
• powering an analog-to-digital converter (ADC) with the power signal;
• sampling voltages at the first frequency using the ADC;
• and
• transmitting the sampled voltages across an electrical isolation barrier toward a device output pin.