Sub-sampling phase-locked loop
AssigneeHuawei Technologies Co., Ltd.
InventorAnders JAKOBSSON
Life of this patent
Estimating the term…
Abstract
A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.
Claims20
A sub-sampling phase-locked loop comprising:
- a digital-to-time converter (DTC),
- a sampler module,
- an interpolator, and
- an oscillator which is voltage controlled;
- wherein the digital-to-time converter is configured to provide a first delay signal and a second delay signal to the sampler module,
- wherein the sampler module is configured to provide a first sample of an oscillator output signal based on the first delay signal and a second sample of the oscillator output signal based on the second delay signal;
- wherein the interpolator is configured to provide a sampler signal by interpolating the first sample and the second sample;
- and
- wherein the oscillator is configured to control the oscillator output signal based on the sampler signal, and provide the oscillator output signal to the sampler module.
A method, implemented by a sub-sampling phase-locked loop, the method comprising:
- providing, by a digital-to-time converter (DTC) of the sub-sampling phase-locked loop, a first delay signal and a second delay signal, to a sampler module of the sub-sampling phase-locked loop,
- providing, by the sampler module of the sub-sampling phase-locked loop, a first sample of an oscillator output signal based on the first delay signal and a second sample of the oscillator output signal based on the second delay signal;
- providing, by an interpolator of the sub-sampling phase-locked loop, a sampler signal by interpolating the first sample and the second sample;
- and
- controlling and providing, by an oscillator of the sub-sampling phase-locked loop, the oscillator output signal based on the sampler signal to the sampler module of the sub-sampling phase-locked loop.
Dependencies are inferred from the claim text.