Clock data recovery circuit, apparatus including the same and method for recovery clock and data
AssigneeSamsung Electronics Co., Ltd.
InventorsJUNG-PIL LIM, KYUNG-HO RYU, JAE-SUK YU, JAE-YOUL LEE, DONG-MYUNG LEE, HYUN-WOOK LIM
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Abstract
A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.
Claims20
A clock data recovery circuit that receives an input data signal including an embedded clock, the clock data recovery circuit comprising:
- a clock recovery circuit configured to generate a recovery clock signal from the input data signal based on a first window signal and to generate a second window signal synchronized with the recovery clock signal from the first window signal;
- a delayed locked loop circuit configured to detect a unit interval corresponding to one bit of the input data signal based on the recovery clock signal and to generate a third window signal by delaying the second window signal based on the unit interval;
- and
- a window generating circuit configured to generate the first window signal based on the third window signal and the recovery clock signal, so that a phase of the recovery clock signal is identical to a phase of the third window signal.
A clock data recovery circuit that receives an input data signal including an embedded clock, the clock data recovery circuit comprising:
- a clock recovery circuit configured to generate a recovery clock signal by extracting periodic edges from the input data signal based on a first window signal and to generate a second window signal synchronized with the recovery clock signal from the first window signal;
- a delayed locked loop circuit configured to detect a unit interval corresponding to one bit of the input data signal based on the recovery clock signal and to generate a plurality of delayed clock signals by delaying the recovery clock signal;
- and
- a window generating circuit configured to generate the first window signal based on the second window signal and a delayed clock signal from among the plurality of delayed clock signals, so that a phase of the second window signal is identical to a phase of the delayed clock signal.
A method of recovering a clock and data from an input data signal including an embedded clock, the method comprising:
- generating a recovery clock signal from the input data signal based on a first window signal;
- detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal;
- delaying a signal synchronized with the recovery clock signal based on the unit interval to provide a delayed signal;
- and
- generating the first window signal based on the delayed signal.
Dependencies are inferred from the claim text.