Level shifter circuit generating bipolar clock signals

A level shifter circuit comprising:

• a first transistor pair coupled at a first input node;
• a second transistor pair coupled at a second input node, wherein the first and second transistor pairs couple at a first node, a second node, a third node, and a fourth node;
• a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal;
• a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal;
• and
• a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node, wherein the clock generation circuit is configured to generate a first clock at the first node, a second clock at the second node, a third clock at the third node, and a fourth clock at the fourth node.