Crystal oscillator interconnect architecture with noise immunity

An apparatus comprising:

• a high pass filter;
• a pair of AC coupling capacitors coupled to the high pass filter;
• a low pass filter coupled to the pair of AC coupling capacitors;
• and
• an analog to digital converter (ADC) coupled to the low pass filter.

An apparatus comprising:

• a crystal oscillator having a feedback network;
• an amplification circuitry coupled to the feedback network;
• a filter coupled to an output of the amplification circuitry, wherein the filter comprises a high-pass filter and a low-pass filter, wherein the high-pass filter is coupled the low-pass filter;
• and
• an analog-to-digital converter (ADC) coupled to an output of the filter.

A system comprising:

• a memory;
• a processor coupled to the memory;
• a clock synthesizer having a reference clock node to receive a reference clock;
• a reference clock generator coupled to the clock synthesizer, wherein the reference clock generator is to provide the reference clock, and wherein the reference clock generator comprises:
• a high pass filter;
• a pair of AC coupling capacitors coupled to the high pass filter;
• a low pass filter coupled to the pair of AC coupling capacitors;
• and
• an analog to digital converter (ADC) coupled to the low pass filter;
• and
• a wireless interface to allow the processor to communicate with another device.

The system of claim 21, wherein the oscillator comprises:

• a crystal having an input and an output;
• a first interconnect line having first and second ends, wherein the first end is coupled to the input;
• a second interconnect line having first and second ends, wherein the first end is coupled to the output;
• a first capacitor coupled to the input and ground;
• and
• a second capacitor coupled to the second end of the second interconnect line.