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US 2019/0157461 A1Published application
Semiconductor device and method for manufacturing the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
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Abstract
An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
Claims7
(canceled)
A semiconductor device comprising:
- a gate electrode layer;
- a gate insulating layer over the gate electrode layer;
- a semiconductor layer over the gate insulating layer;
- a first layer over the semiconductor layer;
- a second layer over the semiconductor layer;
- a source electrode layer electrically connected to the semiconductor layer through the first layer;
- and
- a drain electrode layer electrically connected to the semiconductor layer through the second layer,
- wherein each of the source electrode layer and the drain electrode layer includes a stacked structure of a first conductive layer and a second conductive layer,
- wherein one of the first conductive layer and the second conductive layer includes copper,
- wherein, in plan view:
- the semiconductor layer includes a first region projected beyond a periphery of the first layer,
- the first layer includes a region projected beyond a periphery of the source electrode layer,
- the semiconductor layer includes a second region projected beyond a periphery of the second layer, and
- the second layer includes a region projected beyond a periphery of the drain electrode layer, and
- wherein, in the semiconductor layer:
- a thickness of the first region is smaller than a thickness of a region overlapping with the first layer, and
- a thickness of the second region is smaller than a thickness of a region overlapping with the second layer.
15 more elements
A semiconductor device comprising:
- a gate electrode layer;
- a gate insulating layer over the gate electrode layer;
- a semiconductor layer over the gate insulating layer;
- a first layer over the semiconductor layer;
- a second layer over the semiconductor layer;
- a source electrode layer electrically connected to the semiconductor layer through the first layer;
- and
- a drain electrode layer electrically connected to the semiconductor layer through the second layer,
- wherein each of the source electrode layer and the drain electrode layer includes a stacked structure of a first conductive layer and a second conductive layer,
- wherein one of the first conductive layer and the second conductive layer includes copper,
- wherein the semiconductor layer includes a channel formation region overlapping with the gate electrode layer,
- wherein, in plan view:
- the semiconductor layer includes a first region projected beyond a periphery of the first layer,
- the first layer includes a region projected beyond a periphery of the source electrode layer,
- the semiconductor layer includes a second region projected beyond a periphery of the second layer, and
- the second layer includes a region projected beyond a periphery of the drain electrode layer, and
- wherein the semiconductor layer has a depression in the channel formation region.
14 more elements
A semiconductor device comprising:
- a gate electrode layer;
- a gate insulating layer over the gate electrode layer;
- a semiconductor layer over the gate insulating layer;
- a first layer over the semiconductor layer;
- a second layer over the semiconductor layer;
- a source electrode layer electrically connected to the semiconductor layer through the first layer;
- and
- a drain electrode layer electrically connected to the semiconductor layer through the second layer,
- wherein each of the source electrode layer and the drain electrode layer includes a stacked structure of a first conductive layer and a second conductive layer,
- wherein one of the first conductive layer and the second conductive layer includes copper,
- wherein the semiconductor layer includes a channel formation region overlapping with the gate electrode layer,
- wherein, in plan view:
- the semiconductor layer includes a first region projected beyond a periphery of the first layer,
- the first layer includes a region projected beyond a periphery of the source electrode layer,
- the semiconductor layer includes a second region projected beyond a periphery of the second layer, and
- the second layer includes a region projected beyond a periphery of the drain electrode layer,
- wherein the semiconductor layer has a depression in the channel formation region, and
- wherein, in the semiconductor layer:
- a thickness of the first region is smaller than a thickness of a region overlapping with the first layer, and
- a thickness of the second region is smaller than a thickness of a region overlapping with the second layer.
17 more elements
Dependencies are inferred from the claim text.