US 2019/0157455 A1 · METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH STRAINED SILICON STRUCTURE

Abstract

A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

Claims11

Dependent claims

A method for fabricating a semiconductor device, comprising:

providing a substrate;
forming a gate on the substrate;
forming a spacer on a sidewall of the gate;
forming a hard mask layer on the spacer;
forming a recessed region in the substrate and adjacent to the hard mask layer;
forming an epitaxial layer in the recessed region;
altering particle defects on the hard mask layer from a granular structure to an amorphous structure;
performing an annealing process to repair damages to the epitaxial layer;
and
removing the hard mask layer and the particle defects on the hard mask layer.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/820,443Filed 22 Nov 2017

Published

23 May 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10P 95/00
Generic processes or apparatus for manufacture or treatments not covered by the
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 62/151
Source or drain regions of field-effect devices: of igfets

Method for fabricating semiconductor device with strained silicon structure

Life of this patent

Method for fabricating semiconductor device with strained silicon structure

Life of this patent

Abstract

Claims11