Semiconductor device with selectively etched surface passivation

A heterostructure field effect transistor (HFET) device comprising:

• a semiconductor substrate comprising a base substrate and a Group III nitride semiconductor epitaxial layer supported by the base substrate and configured to include a channel, the semiconductor substrate further comprising at least one contact region formed along a surface of the semiconductor substrate and at least one isolation region defining an active area along a surface of the semiconductor substrate;
• an ohmic contact supported by the semiconductor substrate, disposed over the contact regions in the active area, and in ohmic contact with at least one contact region for current flow through the channel;
• a first dielectric layer supported by the semiconductor substrate and extending across the active area;
• and
• a second dielectric layer disposed between the first dielectric layer and the surface of the semiconductor substrate in a first portion of the active area;
• wherein the first and second dielectric layers comprise respective openings in which the ohmic contact is disposed;
• wherein the second dielectric layer is patterned such that the first dielectric layer passivates the surface of the semiconductor substrate in a second portion of the active area.

A method of fabricating a semiconductor device, the method comprising:

• defining an active area of the semiconductor device along a surface of a semiconductor substrate;
• forming an implant mask over a surface of the semiconductor substrate;
• patterning the implant mask to define contact regions;
• ion implanting a dopant species to create contact regions;
• activating the dopant species;
• depositing an etch stop dielectric layer on the surface in the active area;
• depositing a passivation layer on the etch stop dielectric layer;
• defining an ohmic contact area by dry etching the passivation layer;
• removing the etch stop dielectric layer in the ohmic contact area via a wet etch;
• and
• forming an ohmic contact in the ohmic contact area,
• wherein forming the ohmic contact comprises implementing an anneal procedure at an anneal temperature lower than a crystallization temperature of the etch stop dielectric layer.