Single column compound semiconductor bipolar junction transistor with all-around base
AssigneeInternational Business Machines Corporation
InventorsKarthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
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Abstract
A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.
Claims20
A single column bipolar junction transistor device, comprising:
- a semiconductor substrate;
- a dielectric layer on the semiconductor substrate;
- a trench extending through the dielectric layer;
- a vertical column extending from the semiconductor substrate, the vertical column including:
- a heavily doped III-V compound semiconductor collector having a first conductivity type,
- a heavily doped III-V compound semiconductor emitter having the first conductivity type, and
- a doped III-V compound semiconductor sublayer having a second conductivity type opposite to the first conductivity type, the doped III-V compound semiconductor sublayer being between and directly contacting the collector and the emitter;
- a III-V compound semiconductor buffer layer extending through the trench and directly contacting the vertical column and the semiconductor substrate;
- a doped extrinsic base completely surrounding and directly contacting the doped III-V compound semiconductor sublayer;
- a collector contact electrically connected to the collector;
- an emitter contact electrically connected to the emitter, and
- a base contact electrically connected to the extrinsic base.
A method of fabricating a structure including single column bipolar junction transistor device, comprising:
- obtaining a structure including:
- a semiconductor substrate,
- a dielectric layer on the substrate, and
- a vertically extending trench extending through the dielectric layer, the vertically extending trench being configured for aspect ratio trapping;
- forming a vertical column of III-V compound semiconductor material within the vertically extending trench by:
- epitaxially growing a III-V compound semiconductor buffer layer on the substrate,
- epitaxially growing a heavily doped III-V compound semiconductor bottom sublayer having a first conductivity type on the buffer layer,
- epitaxially growing a doped III-V compound semiconductor middle sublayer having a second conductivity type opposite to the first conductivity type on the bottom sublayer;
- and
- epitaxially growing a heavily doped III-V compound semiconductor top sublayer having the first conductivity type on the middle sublayer;
- recessing the dielectric layer to expose at least the top, middle and bottom sublayers of the vertical column;
- forming a plurality of sacrificial layers over the recessed dielectric layer, the plurality of sacrificial layers including a bottom sacrificial layer around the bottom sublayer, a middle sacrificial layer around the middle sublayer and a top sacrificial layer around the top sublayer;
- removing the middle sacrificial layer to form a space between the bottom and top sacrificial layers, and
- epitaxially growing a doped extrinsic base on the middle sublayer and within the space between the bottom and top sacrificial layers, the extrinsic base extending entirely around the middle sublayer.
The method of claim 12, wherein the substrate consists essentially of silicon.
Dependencies are inferred from the claim text.