Semiconductor device gate spacer structures and methods thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
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Abstract
A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
Claims22
A semiconductor device, comprising:
- a substrate having a channel region, the substrate further including a source/drain (S/D) region, the S/D region having a first doped S/D region adjacent to the channel region and a second doped S/D region adjacent to the first doped S/D region, wherein the second doped S/D region is more heavily doped than the first doped S/D region;
- a gate stack over the channel region;
- a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride;
- a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion, the first vertical portion offset from the second doped S/D region and in physical contact with the first doped S/D region, the first horizontal portion in physical contact with both the first doped S/D region and the second doped S/D region;
- and
- a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
(canceled)
A semiconductor device, comprising:
- a substrate having source/drain (S/D) regions with a channel region interposed between the S/D regions;
- a gate stack over the channel region;
- a dielectric layer covering sidewalls of the gate stack, the dielectric layer including a nitride;
- a spacer layer covering sidewalls of the dielectric layer, the spacer layer including an oxide, wherein a sidewall of the spacer layer includes an upper sidewall, a horizontal surface, and an lower sidewall, thereby forming a step profile;
- and
- a contact etch stop (CES) layer covering the sidewall of the spacer layer, the CES layer including a nitride, and
- wherein the S/D regions include a first doped S/D region and a second doped S/D region that is more heavily doped than the first doped S/D region, wherein the upper sidewall is directly above the first doped S/D region, and the lower sidewall is directly above the second doped S/D region.
(canceled)
A method, comprising:
- forming a gate structure on a substrate;
- forming a seal spacer covering the gate structure and a portion of the substrate;
- removing a portion of the seal spacer to expose the portion of the substrate;
- forming a gate spacer covering the seal spacer and directly on the exposed portion of the substrate, the gate spacer having a first vertical portion and a first horizontal portion;
- forming a hard mask layer covering the gate spacer, the hard mask layer having a second vertical portion and a second horizontal portion;
- removing the second horizontal portion of the hard mask layer and part of the first horizontal portion of the gate spacer that is under the second horizontal portion of the hard mask layer;
- and
- forming a contact etch stop (CES) layer covering the gate spacer.
Dependencies are inferred from the claim text.