US 2019/0157418 A1 · TRANSISTOR WITH DUAL SPACER AND FORMING METHOD THEREOF

Abstract

A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Claims26

Dependent claims

A transistor with dual spacers, comprising:

a gate disposed on a substrate, wherein the gate comprises a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate;
a first dual spacer disposed on the gate dielectric layer beside the gate, wherein the first dual spacer comprises a first inner spacer and a first outer spacer;
a second inner spacer having an L-shaped profile disposed on the gate dielectric layer beside the first dual spacer.

Dependencies are inferred from the claim text.

Facts

Application

15/846,150Filed 18 Dec 2017

Priority

CN 201711146633.317 Nov 2017

Published

23 May 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs

Transistor with dual spacer and forming method thereof

Life of this patent

Transistor with dual spacer and forming method thereof

Life of this patent

Abstract

Claims26