Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts

A method for fabricating a semiconductor device, comprising:

• forming a field effect transistor (FET) device on a semiconductor substrate, the FET device comprising a source/drain layer, and a gate structure comprising a gate electrode layer, a gate capping layer, and a gate sidewall spacer;
• forming a first interlevel dielectric (ILD) layer which encapsulates the FET device;
• forming a gate contact opening in the first ILD layer and the gate capping layer to expose a portion of the gate electrode layer of the gate structure, wherein a portion of the gate contact opening has width that is greater than a width of the gate structure;
• forming an insulating spacer on vertical sidewalls of the gate contact opening in the first ILD layer;
• forming a vertical gate contact in the gate contact opening in contact with the exposed portion of the gate electrode layer of the gate structure of the FET device;
• forming a source/drain contact opening in the first ILD layer down to the source/drain layer of the FET device, wherein the source/drain contact opening exposes a portion of the insulating spacer formed on the vertical sidewalls of the gate contact opening;
• and
• forming a vertical source/drain contact in the source/drain contact opening in contact with the source/drain layer, wherein the exposed portion of the insulating spacer serves to electrically insulate the vertical gate contact from the vertical source/drain contact.