Middle-of-line (mol) capacitance reduction for self-aligned contact in gate stack

A method comprising:

• forming a middle-of-line (MOL) oxide layer in a semiconductor structure, the MOL oxide layer including a plurality of gate stacks formed on a substrate;
• forming a first nitride layer over a first silicide in the MOL oxide layer;
• forming a second nitride layer over a second silicide in the MOL oxide layer;
• forming a first self-aligned contact area (CA) element within the first nitride layer and a second self-aligned CA element within the second nitride layer;
• masking the first and the second self-aligned CA elements;
• selectively recessing the MOL oxide layer on a first side and a second side of each of the first and the second self-aligned CA elements leaving remaining portions of the MOL oxide layer on the first nitride layer, the second nitride layer, a first nitride and a second nitride;
• etching a nitride cap of each gate stack of the plurality of gate stacks;
• removing the mask from the first and second self-aligned CA elements;
• depositing an air-gap oxide layer introducing one or more air-gaps in the deposited air-gap oxide layer;
• and
• reducing the air gap oxide layer to the first and the second self-aligned CA elements and the first and the second nitride layers.