Test circuit block, variable resistance memory device including the same, and method of forming the variable resistance memory device
AssigneeSK hynix Inc.
InventorsSeok Joon KANG, Ho Seok EM
Life of this patent
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Abstract
A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line.
Claims20
A test circuit block comprising:
- a first signal line;
- a second signal line;
- a high resistive path unit connected between the first signal line and the second signal line;
- and
- a low resistive path unit having a resistance lower than a resistance of the high resistive path unit, the low resistive path unit selectively connected with the high resistive path unit in parallel, between the first signal line and the second signal line.
A variable resistance memory device comprising:
- a semiconductor substrate;
- a core circuit block including a sense amplifier and a test circuit block positioned over the semiconductor substrate;
- and
- a memory cell array stacked on the core circuit block, the memory cell array including a plurality of bit lines, a plurality of word lines and resistive memory cells connected between the bit lines and the word lines,
- wherein the test circuit block comprises:
- a test bit line connected with any one of the bit lines;
- a test word line connected with any one of the word lines;
- a high resistive path unit connected between the any one of the bit lines and the anyone of the word lines when a test mode signal is enabled;
- and
- a low resistive path unit selectively connected in parallel with the high resistive path unit between the test bit line and the test word line.
A method of forming a variable resistance memory device, the method comprising:
- forming a core circuit on a semiconductor substrate, the core circuit including a test circuit block formed by modeling a memory cell;
- verifying the core circuit using the test circuit block;
- correcting the core circuit when an error is generated in the core circuit;
- and
- forming a memory cell array including a plurality of memory cells on the core circuit.
Dependencies are inferred from the claim text.