Semiconductor memory device including a selection element pattern confined to a hole
AssigneeSK hynix Inc.
InventorJong Chul LEE
Life of this patent
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Abstract
An electronic device having a semiconductor memory device is provided. The semiconductor memory device may include a lower interlayer insulating layer having a hole; an upper interlayer insulating layer disposed on the lower interlayer insulating layer; and a memory cell stack including a lower element and an upper element, the lower element being confined to the hole of the lower interlayer insulating layer, the upper element being surrounded by the upper interlayer insulating layer. The lower element may include a lower electrode and a selection element pattern disposed on the lower electrode. The upper element may include a memory pattern disposed on the selection element pattern and an upper electrode disposed on the memory pattern.
Claims20
An electronic device including a semiconductor memory device, the semiconductor memory device comprising:
- a lower interlayer insulating layer having a hole;
- an upper interlayer insulating layer disposed on the lower interlayer insulating layer;
- and
- a memory cell stack including a lower element and an upper element, the lower element being confined to the hole of the lower interlayer insulating layer, the upper element being surrounded by the upper interlayer insulating layer,
- wherein the lower element includes a lower electrode and a selection element pattern disposed on the lower electrode,
- wherein the upper element includes a memory pattern disposed on the selection element pattern and an upper electrode disposed on the memory pattern.
An electronic device including a semiconductor memory device, the semiconductor memory device comprising:
- a lower interlayer insulating layer having a hole;
- is a lower spacer disposed in the hole of the lower interlayer insulating layer;
- a lower pillar disposed in the hole and confined by the lower spacer;
- an upper pillar disposed on the lower pillar;
- an upper spacer disposed on a sidewall of the upper spacer;
- and
- an upper interlayer insulating layer surrounding the upper spacer and being disposed on the lower interlayer insulating layer,
- wherein the lower pillar includes a lower electrode and a selection element pattern disposed on the lower electrode,
- wherein the upper pillar includes a memory pattern and an upper electrode disposed on the memory pattern;
- and
- wherein a horizontal width of the upper pillar is greater than a horizontal width of the lower pillar.
Dependencies are inferred from the claim text.