Back-channel-etched tft substrate and manufacturing method thereof

6:

• A back-channel-etched (BCE) thin film transistor (TFT) substrate, comprising:
• a base substrate, a gate disposed on the base substrate, a gate insulating layer disposed on the base substrate and the gate, an active layer disposed on the gate insulating layer, a source and a drain disposed at interval on the active layer, and a passivation layer disposed on the source, the drain, and the active layer;
• the source and the drain being formed by patternizing a source-drain material layer, the source-drain material layer comprising:
• a first source-drain material layer disposed on the active layer, a second source-drain material layer disposed on the first source-drain material, and a third source-drain material layer disposed on the second source-drain material layer;
• the first source-drain material layer comprising Mo, the second source-drain material layer comprising Cu, and the third source-drain material layer being a conductorized IGZO film.

11:

• A manufacturing method of back-channel-etched (BCE) thin film transistor (TFT) substrate, comprising:
• providing a base substrate, depositing metal on the base substrate and etching the metal to form a gate, forming a gate insulating layer on the base substrate and the gate;
• forming an active layer on the gate insulating layer;
• depositing a source-drain material layer on the active layer and the gate insulating layer, the source-drain material layer comprising:
• a first source-drain material layer disposed on the active layer and the gate insulating layer, a second source-drain material layer disposed on the first source-drain material, and a third source-drain material layer disposed on the second source-drain material layer;
• the first source-drain material layer comprising Mo, the second source-drain material layer comprising Cu, and the third source-drain material layer being a conductorized IGZO film;
• defining a source-drain pattern region and a non-pattern region surrounding the source-drain pattern region on the source-drain material layer, with the source-drain pattern region comprising a source predetermined pattern region, a drain predetermined pattern region, and a source-drain spacer located between the source predetermined pattern region and the drain-target pattern region;
• forming a photo-resist layer on the source-drain material layer, patternizing the photo-resist layer with a half-tone mask, removing the portion of the photo-resist layer corresponding to the non-pattern region, and thinning the portion of the photo-resist layer corresponding to the source-drain spacer;
• removing the non-pattern region of the source-drain material layer by using a fluorine-containing etching solution;
• performing an ashing process on remaining photo-resist layer to remove the portion of the photo-resist layer corresponding to the source-drain spacer, thinning the portions of the photo-resist layer corresponding to the source predetermined pattern region and the drain predetermined pattern region;
• removing the source-drain spacer of the source-drain material layer by etching with a fluorine-free etchant;
• stripping off remaining photo-resist layer to obtain the source and drain disposed at interval;
• forming a passivation layer on the source, the drain, the active layer and the gate insulating layer;
• wherein the conductorized IGZO film being prepared by magnetron sputtering;
• during the magnetron sputtering process, no oxygen being added into the reaction chamber, and the molar ratio of indium, gallium, zinc, and oxide in the obtained IGZO film being In:Ga:Zn:O=1:1:1:X, where X being less than 4;
• wherein the gate comprising a first gate layer disposed on the base substrate and a second gate layer disposed on the first gate layer, the material of first gate layer comprising Mo, and the material of the second gate layer comprising Cu;
• wherein the material of the active layer comprising IGZO;
• wherein the material of the passivation layer comprising SiOx.