Ips thin-film transistor array substrate and manufacturing method thereof

An in-plane switching (IPS) thin-film transistor (TFT) array substrate, comprising:

• a backing plate;
• a gate electrode, a scan line, a pixel electrode, and a common electrode that are arranged on the backing plate, wherein the scan line and the gate electrode are connected to each other;
• a gate insulation layer that is arranged on the gate electrode, the scan line, the pixel electrode, and the common electrode, wherein the gate insulation layer is formed with a first through hole that is located above and corresponds to the pixel electrode and a second through hole that is located above and corresponds to the common electrode;
• an active layer that is arranged on the gate insulation layer and is located above and corresponds to the gate electrode;
• and
• a source electrode and a drain electrode that are arranged on the active layer and the gate insulation layer and a data line and a common electrode line that are arranged on the gate insulation layer, wherein the source electrode and the drain electrode are respectively in contact engagement with two sides of the active layer;
• the data line and the source electrode are connected to each other;
• the drain electrode is connected through the first through hole of the gate insulation layer to the pixel electrode;
• and the common electrode line is connected through the second through hole of the gate insulation layer to the common electrode.

A method for manufacturing an in-plane switching (IPS) thin-film transistor (TFT) array substrate, comprising the following steps:

• S1:
• providing a backing plate and forming a gate electrode, a scan line, a pixel electrode, and a common electrode on the backing plate with a first mask-involved operation, wherein the scan line and the gate electrode are connected to each other;
• S2:
• depositing a gate insulation layer on the gate electrode, the scan line, the pixel electrode, the common electrode, and the backing plate, depositing a semiconductor layer on the gate insulation layer, and subjecting the gate insulation layer and the semiconductor layer to patterning treatment with a second mask-involved operation to form a first through hole and a second through hole in the gate insulation layer and an active layer located above and corresponding to the gate electrode, wherein the first through hole and the second through hole are respectively corresponding to and located above the pixel electrode and the common electrode;
• and
• S3:
• depositing a source-drain metal layer on the active layer and the gate insulation layer and subjecting the source-drain metal layer to patterning treatment with a third mask-involved operation so as to form a source electrode, a drain electrode, a data line, and a common electrode line, wherein the source electrode and the drain electrode are respectively in contact engagement with two sides of the active layer;
• the data line and the source electrode are connected to each other;
• the drain electrode is connected through the first through hole of the gate insulation layer to the pixel electrode;
• and the common electrode line is connected through the second through hole of the gate insulation layer to the common electrode;
• wherein Step S1 comprises:
• S11:
• depositing a first metal layer on the backing plate with physical vapor deposition;
• S12:
• subjecting the first metal layer to patterning treatment with the first mask-involved operation to form a predetermined gate electrode pattern and a predetermined scan line pattern, and the pixel electrode and the common electrode;
• and
• S13:
• coating a second metal layer on the predetermined gate electrode pattern and the predetermined scan line pattern to form the gate electrode and the scan line, wherein the second metal layer has electrical conductance greater than electrical conductance of the first metal layer;
• wherein the first metal layer is formed of a material comprising one or multiple ones of molybdenum, molybdenum-titanium alloy, indium tin oxide, molybdenum-tungsten alloy, molybdenum-tantalum alloy, and molybdenum-niobium alloy;
• wherein the second metal layer is formed of a material comprising copper;
• and
• wherein an operation of coating the second metal layer on the predetermined gate electrode pattern and the predetermined scan line pattern comprises electrical plating.