Ffs type tft array substrate and the manufacturing method thereof

A fringe field switching (FFS) type thin film transistor (TFT) array substrate, comprising:

• a base substrate;
• a gate electrode, a scanning line, a common electrode, and a common electrode line being disposed on the base substrate;
• wherein the gate electrode is connected with the scanning line, and the common electrode is connected with the common electrode line;
• a gate insulating layer being disposed on the gate electrode, the scanning line, the common electrode, the common electrode line and the base substrate;
• an active layer being disposed on the gate insulating layer and corresponding onto the gate electrode;
• a source electrode and a drain electrode being disposed on the active layer and the gate insulating layer, and a data line being disposed on the gate insulating layer;
• wherein, the source electrode and the drain electrode are respectively in contact with the active layer;
• the data line is connected with the source electrode;
• a passivation layer being disposed on the source electrode, the drain electrode, the data line, the active layer, and the gate insulating layer;
• a first through hole being disposed on the passivation layer and corresponding onto the drain electrode;
• a pixel electrode being disposed on the passivation layer;
• wherein the pixel electrode is connected with the drain electrode via the first through hole located on the passivation layer;
• or
• a passivation layer being disposed on the source electrode, the drain electrode, the data line, the active layer, and the gate insulating layer, and a planer layer being disposed on the passivation layer, a second through hole being disposed on the passivation layer and the planer layer and corresponding onto the drain electrode;
• a pixel electrode being disposed on the planer layer;
• wherein the pixel electrode is connected with the drain electrode via the second through hole located on the passivation layer and the planer layer;
• wherein the gate electrode and the scanning line have a dual-layer structure comprising a layer of a first material and a second layer of a second material disposed on a top of the layer of the first material layer, and common electrode and the common electrode line have a single-layer structure comprising a layer of the first material.

A manufacturing method for a fringe field switching (FFS) type thin film transistor (TFT) array substrate, comprising:

• providing a base substrate, and forming a gate electrode, a scanning line, a common electrode and a common electrode line on the base substrate by using a first photomask process;
• wherein the gate electrode is connected with the scanning line, and the common electrode is connected with the common electrode line;
• depositing a gate insulating layer on the gate electrode, the scanning line, the common electrode, the common electrode line and the base substrate, and depositing a semiconductor layer on the gate insulating layer, patterning the semiconductor layer by using a second photomask process, so as to obtain an active layer corresponding onto the gate electrode;
• disposing a source/drain metal layer on the active layer and the gate insulating layer, and patterning the source/drain metal layer by using a third photomask process, so as to obtain a source electrode, a drain electrode, and a data line;
• wherein, the source electrode and the drain electrode are respectively in contact with the active layer;
• the data line is connected with the source electrode;
• forming a passivation layer on the source electrode, the drain electrode, the data line, the active layer, and the gate insulating layer, patterning the passivation layer by using a fourth photomask process, so as to obtain a first through hole located on the passivation layer, the first through hole being corresponding onto the drain electrode;
• depositing a second transparent conductive layer on the passivation layer, and patterning the second transparent conductive layer by using a fifth photomask process, so as to obtain a pixel electrode on the passivation layer;
• wherein the pixel electrode is connected with the drain electrode via the first through hole located on the passivation layer;
• or
• forming a passivation layer on the source electrode, the drain electrode, the data line, the active layer, and the gate insulating layer, and forming a planer layer on the passivation layer, patterning the passivation layer and the planer layer by using a fourth photomask process, so as to obtain a second through hole located on the passivation layer and the planer layer, the second through hole being corresponding onto the drain electrode;
• depositing a second transparent conductive layer on the planer layer, and patterning the second transparent conductive layer by using a fifth photomask process, so as to obtain a pixel electrode on the planer layer;
• wherein the pixel electrode is connected with the drain electrode via the second through hole located on the passivation layer and the planer layer;
• wherein in the step of forming a gate electrode, a scanning line, a common electrode and a common electrode line on the base substrate by using a first photomask process further comprises:
• depositing a first transparent conductive layer on the base substrate, patterning the first transparent conductive layer by using the first photomask process, so as to obtain a predetermined pattern of the gate electrode and a predetermined pattern of the scanning line, the common electrode, and the common electrode line;
• plating a first metal layer on the predetermined pattern of the gate electrode and the predetermined pattern of the scanning line, so as to obtain the gate electrode and the scanning line;
• wherein a conductivity of the first metal layer is greater than a conductivity of the first transparent conductive layer;
• wherein the first transparent conductive layer is selected from the group consisting of transparent conductive metal oxide;
• and the first metal layer is selected from the group consisting of copper;
• wherein a process of plating a first metal layer on the predetermined pattern of the gate electrode and the predetermined pattern of the scanning line is an electroplating process;
• wherein the passivation layer is selected from the group consisting of silicon oxide and silicon nitride, and the planer layer is selected from the group consisting of an organic photoresist material;
• and
• wherein the gate electrode and the scanning line have a dual-layer structure comprising a layer of a first material and a second layer of a second material disposed on a top of the layer of the first material layer, and common electrode and the common electrode line have a single-layer structure comprising a layer of the first material, the layer of the first material comprising the first transparent conductive layer, the layer of the second material comprising the first metal layer.