Vertical memory devices and methods of manufacturing the same

A vertical memory device, comprising:

• first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate;
• a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region;
• a channel extending through the gate electrode structure and the second and third impurity regions on the substrate in the first direction, at least a portion of the channel contacting the second impurity region;
• a charge storage structure covering a portion of an outer sidewall of the channel;
• and
• a support pattern between the first and third impurity regions, the support pattern contacting a sidewall of the second impurity region and an edge lower surface of the third impurity region.

A vertical memory device, comprising:

• an impurity region structure on a substrate, the impurity region structure including polysilicon doped with impurities;
• a gate electrode structure including gate electrodes spaced apart from each other in a first direction on the impurity region structure, the first direction being substantially parallel to an upper surface of the substrate;
• a channel extending through the gate electrode structure and at least a portion of the impurity region structure on the substrate in the first direction, a first portion of an outer sidewall of the channel directly contacting the impurity region structure;
• and
• a charge storage structure covering a second portion of the outer sidewall and a lower surface of the channel, the second portion not directly contacting the impurity region structure.