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US 2019/0157292 A1Published application
Semiconductor memory device including a capacitor
AssigneeSamsung Electronics Co., Ltd.
InventorsCHANHO KIM, PANSUK KWAK, CHAEHOON KIM, HONGSOO JEON, JEUNGHWAN PARK, BONGSOON LIM
Life of this patent
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Abstract
At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
Claims20
A nonvolatile memory device comprising:
- a memory cell array formed in a first area of a substrate;
- and
- a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines,
- wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate,
- wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises
- latches connected to a sensing node, and
- a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines,
- wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node,
- wherein the capacitor comprises
- at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and
- at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
8 more elements
A nonvolatile memory device comprising:
- a memory cell array formed in a first area of a substrate;
- and
- a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines,
- wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate,
- wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines,
- wherein each of the page buffers comprises
- latches connected to a sensing node,
- a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, and
- a capacitor connected to the sensing node, and
- wherein the capacitor comprises
- at least one first contact to which a sensing voltage of the sensing node is supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings;
- and
- at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
10 more elements
A nonvolatile memory device comprising:
- a memory cell array formed in a first area of a substrate;
- and
- a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines,
- wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate,
- wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines,
- wherein each of the page buffers comprises
- latches connected to a sensing node,
- a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, and
- a capacitor configured to provide a capacitance to each of the page buffers,
- wherein the capacitor comprises
- at least one first contact having a second height corresponding to a first height of each of the cell strings, and
- at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
9 more elements
Dependencies are inferred from the claim text.