Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device, comprising:

• a substrate including a cell array region and a connection region;
• an electrode structure provided on the substrate to extend in a first direction and to include electrodes that are vertically stacked on the substrate, each of the electrodes comprising a respective pad portion from among a plurality of pad portions which are stacked on the connection region to form a staircase structure;
• a plurality of cell vertical structures provided on the cell array region and configured to penetrate the electrode structure;
• a plurality of cell contact plugs, each of the plurality of cell contact plugs being coupled to a corresponding one from among the plurality of pad portions, a top surface of each of the plurality of cell contact plugs having a first length and a second width that less than the first length;
• and
• a plurality of dummy vertical structures provided on the connection region and configured to penetrate the respective pad portion of each of the electrodes such that a respective subset of the plurality of dummy vertical structures is arranged to surround a corresponding one of the plurality of cell contact plugs,
• wherein the plurality of dummy vertical structures comprises a first dummy vertical structure, which is spaced apart from the cell array region by a first distance, and a second dummy vertical structure, which is spaced apart from the cell array region by a second distance that is larger than the first distance, and
• a width of the second dummy vertical structure is larger than a width of the first dummy vertical structure.