Method of ONO Stack Formation
AssigneeCypress Semiconductor Corporation
InventorKrishnaswamy Ramkumar
Life of this patent
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Abstract
A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.
Claims21
1-20. (canceled)
A method, comprising:
- forming a dielectric stack including a layer comprising nitride on a substrate;
- patterning the dielectric stack to form a gate stack of a non-volatile memory (NVM) transistor in a first region of the substrate while concurrently removing the dielectric stack in a second region of the substrate;
- and
- performing a two-step oxidation process to oxidize at least a portion of the layer comprising nitride to form a blocking oxide on the gate stack of the NVM transistor while concurrently forming a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region,
- wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the two-step gate oxidation process.
The method of claim 1, wherein the layer comprising nitride is divided into a first portion and a second portion, wherein the blocking oxide of the gate stack is formed by consuming at least the first portion.
A method, comprising:
- forming a dielectric stack including a charge-trapping layer on a substrate;
- patterning the dielectric stack to form a gate stack of a non-volatile memory (NVM) transistor in a first region of the substrate while concurrently removing the dielectric stack in a second region of the substrate;
- performing an oxidation process to oxidize at least a portion of the dielectric stack to form a blocking oxide on the charge-trapping layer while concurrently forming a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region;
- and
- forming a nitride structure disposed over the gate stack,
- wherein the nitride structure changes energy levels of charge traps configured to be formed in the charge-trapping layer to increase charge retention of the charge-trapping layer.
A method comprising:
- forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric overlying the substrate and a charge-trapping layer overlying the tunneling dielectric;
- patterning the dielectric stack to form a non-volatile (NV) gate stack of a non-volatile memory (NVM) transistor in a first region of the substrate and to remove the dielectric stack from a second region of the substrate;
- and
- performing a two-step oxidation process to concurrently oxidize at least a first portion of the dielectric stack of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region,
- wherein during a first oxidation step of the oxidation process, the dielectric stack of the NV gate stack remains substantially unchanged, both stoichiometrically and chemically.
Dependencies are inferred from the claim text.