Embedded memory using soi structures and methods

An integrated circuit (IC) including a memory device, comprising:

• a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;
• first and second individual source/drain regions arranged in the semiconductor device layer and spaced apart from one another;
• first and second intermediate source/drain regions arranged in the semiconductor device layer and arranged between the first and second individual source/drain regions, the first individual source/drain region being spaced apart from the first intermediate source/drain region by a first control channel region, and the second individual source/drain region being spaced apart from the second intermediate source/drain region by a second control channel region;
• a common source/drain region arranged in the semiconductor device layer and arranged between the first and second intermediate source/drain regions, the first intermediate source/drain region being spaced apart from the common source/drain region by a first select channel region, and the second intermediate source/drain region being spaced apart from the common source/drain region by a second select channel region;
• first and second control gates arranged over the first and second control channel regions, respectively;
• and
• first and second select gates arranged over the first and second select channel regions, respectively;
• wherein the common source/drain region includes a doped region arranged in the handle substrate and an epitaxial semiconductor region extending from near an upper surface of the semiconductor device layer to an upper surface of the doped region.

A method for manufacturing an integrated circuit, the method comprising:

• forming a charge-trapping layer over a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;
• forming a control gate, a select gate, and a dummy gate of a first material and laterally spaced over the semiconductor device layer, wherein the control gate is formed over the charge-trapping layer;
• forming an interlayer dielectric (ILD) layer laterally between the control, select, and dummy gates and with an upper surface that is at a substantially same level with upper surfaces of the control, select, and dummy gates;
• removing the dummy gate to form a gate opening;
• forming a high κ dielectric layer lining the gate opening;
• and
• forming a logic gate of a second material in the gate opening and over the high κ dielectric layer.