Three-Dimensional Semiconductor Devices Including Vertical Structures

The three-dimensional semiconductor device of Claim

• wherein the cell vertical structure further includes a cell core pattern;
• wherein the dummy vertical structure further includes a dummy core pattern including a same material as a material of the cell core pattern and having a greater width than that of the cell core pattern;
• wherein the cell pad layer is on the cell core pattern;
• wherein the cell channel layer is on a side surface of the cell core pattern;
• wherein the upper portion of the buffer region is on the dummy core pattern;
• and
• wherein the lower portion of the buffer region and the dummy channel layer are on a side surface of the dummy core pattern.

A three-dimensional semiconductor device, comprising:

• a gate electrode disposed on a substrate;
• and
• a cell vertical structure and a dummy vertical structure spaced apart from each other while passing through the gate electrode,
• wherein the cell vertical structure includes a cell channel layer opposing the gate electrode and a cell pad layer on the cell channel layer;
• wherein the dummy vertical structure includes a buffer region including a material different from a material of the cell pad layer;
• and
• wherein at least a portion of the buffer region is located at a same level from the substrate as at least a portion of the cell pad layer or at least a portion of the cell channel layer.

A three-dimensional semiconductor device, comprising:

• a substrate including a memory cell array region and a connection region, adjacent to each other;
• gate electrodes sequentially stacked on the memory cell array region and extended to the connection region, the gate electrodes including pad regions on the connection region;
• cell vertical structures on the memory cell array region and passing through the gate electrodes;
• dummy vertical structures on the connection region and passing through the pad regions;
• and
• gate contact plugs on the connection region, on the pad regions, and adjacent to the dummy vertical structures,
• wherein each of the cell vertical structures includes a cell pad layer located at a level higher than that of the gate electrodes and a cell channel layer opposing the gate electrodes;
• and
• wherein at least one among the dummy vertical structures includes a buffer region including a material different from a material of the cell pad layer and a dummy channel layer including a same material as a material of the cell channel layer.