US 2019/0157278 A1Published application

Ferro-electric complementary fet

AssigneeInternational Business Machines Corporation

InventorsDAVID J. FRANK, PAUL M. SOLOMON, XIAO SUN

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Abstract

A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

Claims12

Dependent claims

A field-effect transistor (FET), comprising:

a semiconductor substrate having a first side, a second side opposite from the first side, a third side that connects the first side and the second side, and a fourth side opposite the third side that connects the first side and the second side;
and
a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises
a gate insulating layer;
a ferroelectric material layer disposed on the gate insulating layer;
and
a metal layer disposed on the ferroelectric material layer,
wherein a portion of the upper surface of the substrate that extends from the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first side and the second side, and
a portion of the upper surface of the substrate that extends from the third side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the fourth side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the third side and the fourth side;
self-aligned silicided contacts formed in the n-types contacts and in the p-type contacts;
sidewall spacers from along sides of a stack of the gate insulating layer, the ferroelectric material layer, and the metal layer, and
self-aligned silicided shorts between at least one n-type contact and at least one p-type contact,
wherein a presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

10 more elements

A 2-NAND gate, comprising:

a first field-effect transistor (FET) and a second FET, wherein each FET comprises:
a semiconductor substrate having a first side, a second side opposite from the first side, a third side that connects the first side and the second side, and a fourth side opposite the third side that connects the first side and the second side;
and
a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises
a gate insulating layer;
and
a ferroelectric material layer disposed on the gate insulating laver,
wherein a portion of the upper surface of the substrate that extends from the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first side and the second side, and
a portion of the upper surface of the substrate that extends from the third side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the fourth side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the third side and the fourth side;
and
a self-aligned silicided short between a first n-type contact along the first side of the second FET and a first p-type contact along the third side of the second FET,
wherein
a second n-type contact along the second side of the first FET is connected to ground,
a second p-type contact along the fourth side of the first FET and a second p-type contact along the fourth side of the second FET are connected to a supply voltage,
a second n-type contact along the second side of the second FET is connected to a first n-type contact along the first side of the first FET, and
a first p-type contact along the third side of the first FET and the self-aligned silicided short are connected to an output terminal.

13 more elements

A parasitic p- field-effect transistor (FET), comprising:

a semiconductor substrate having a first side, a second side opposite from the first side, a third side that connects the first side and the second side, and a fourth side opposite the third side that connects the first side and the second side;
and
a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises
a gate insulating layer;
and
a ferroelectric material layer disposed on the gate insulating laver,
wherein a portion of the upper surface of the substrate that extends from the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first side and the second side,
a portion of the upper surface of the substrate that extends from the third side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the fourth side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the third side and the fourth side,
a first n-type contact along the first side is connected to an input terminal,
a first p-type contact along the third side is connected to a supply voltage,
a second n-type contact along the second side is connected to an output terminal, and
a second p-type contact along the fourth side is unconnected, and
wherein a presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

10 more elements

A field-effect transistor (FET), comprising:

a semiconductor substrate having a first side and a second side opposite from the first side;
and
a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises
a gate insulating layer;
and
ferroelectric material layer disposed on the gate insulating layer,
wherein a portion of the upper surface of the substrate that extends from a first portion of the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from a first portion of the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first portion of the first side and the first portion of the second side, and
a portion of the upper surface of the substrate that extends from a second portion of the first side that is adjacent to the first portion of the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from a second portion of the second side that is adjacent to the first portion of the second side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the second portion of the first side and the second portion of the second side,
wherein a presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

6 more elements

Dependencies are inferred from the claim text.