US 2019/0157271 A1 · SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

Claims32

Dependent claims

1-15. (canceled)

A semiconductor device comprising:

an n-type transistor comprising, in a cross section:
(a) a first sidewall insulating film on a substrate,
(b) a first gate insulating film having side surfaces and a bottom surface, the side surfaces of the first gate insulating film connecting with the bottom surface of the first gate insulating film to define a first region, the first gate insulating film comprising a high dielectric constant material,
(c) a first metal gate electrode formed in the first region,
(d) first source/drain regions in the substrate,
(e) a first silicon nitride film formed at an outside of the first metal gate electrode, and
(f) a second silicon nitride film formed over the first metal gate electrode, a portion of the second silicon nitride film contacting with the first metal gate electrode;
a p-type transistor comprising, in the cross section:
(a) a second sidewall insulating film on the substrate,
(b) a second gate insulating film having side surfaces and a bottom surface, the side surfaces of the second gate insulating film connecting with the bottom surface of the second gate insulating film to define a second region, the second gate insulating film comprising the high dielectric constant material,
(c) a second metal gate electrode formed in the second region,
(d) second source/drain regions in the substrate,
(e) a third silicon nitride film formed at an outside of the second metal gate electrode, and
(f) a fourth silicon nitride film formed over the second metal gate electrode, a portion of the fourth silicon nitride film contacting with the second metal gate electrode.

11 more elements

A semiconductor device comprising:

an n-type transistor comprising, in a cross section:
(a) a first sidewall insulating film on a substrate,
(b) a first gate insulating film having side surfaces and a bottom surface, the side surfaces of the first gate insulating film connecting with the bottom surface of the first gate insulating film to define a first region, the first gate insulating film comprising a high dielectric constant material,
(c) a first metal gate electrode formed in the first region,
(d) first source/drain regions in the substrate,
(e) a first silicon nitride film formed at an outside of the first metal gate electrode, and
(f) a second silicon nitride film formed outside of the first silicon nitride film, the second silicon nitride film formed between the first silicon nitride film and an interlaying insulating film;
a p-type transistor comprising, in the cross section,
(a) a second sidewall insulating film on the substrate,
(b) a second gate insulating film having side surfaces and a bottom surface, the side surfaces of the second gate insulating film connecting with the bottom surface of the second gate insulating film to define a second region, the second gate insulating film comprising the high dielectric constant material,
(c) a second metal gate electrode formed in the second region,
(d) second source/drain regions in the substrate,
(e) a third silicon nitride film formed at an outside of the second metal gate electrode, and
(f) a fourth silicon nitride film formed outside of the third silicon nitride film, the fourth silicon nitride film formed between the second silicon nitride film and the interlaying insulating film.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/241,395Filed 7 Jan 2019

Priority

JP 2007-07296820 Mar 2007

Published

23 May 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10D 84/856
Complementary IGFETs, e.g. CMOS: the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs

Family

Application12/530,797Continuation · filed 11 Sep 2009

Application14/669,803Continuation · filed 26 Mar 2015

Application15/154,365Continuation · filed 13 May 2016

Application15/852,041Continuation · filed 22 Dec 2017

Application16/241,395Continuation

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