Vertical field effect transistor (vfet) programmable complementary metal oxide semiconductor inverter

A semiconductor inverter comprising:

• a first vertical semiconductor device having source and drain regions of a first conductivity type;
• a second vertical semiconductor device having source and drain regions of a second conductivity type;
• a common contact electrically connecting an upper source and drain region of the first conductivity type for the first vertical semiconductor device to an upper source and drain region of the second conductivity type for the second vertical semiconductor device, the common electrical contact providing an output for the inverter, the common contact provided by a metal fill formed in a trench that is present in the interlevel dielectric encapsulating the first and second vertical semiconductor device, a first end of metal fill contacting the upper source and drain region for the first vertical semiconductor device, and a second end of the metal fill contacting the upper source and drain region of the second vertical semiconductor device;
• a first gate structure to a first of the first and second vertical semiconductor device having electric contact with an input for the inverter;
• and
• a second gate structure to a second of the first and second vertical semiconductor device provides a floating gate.

A method of forming a semiconductor inverter comprising.

• forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate;
• forming a second conductivity type vertically orientated semiconductor device in a second region of the substrate;
• forming a common contact electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device, the common electrical contact providing an output for the inverter, the common contact provided by a metal fill formed in a trench that is present in the interlevel dielectric encapsulating the first and second vertical semiconductor device, a first end of metal fill contacting the upper source and drain region for the first vertical semiconductor device, and a second end of the metal fill contacting the upper source and drain region of the second vertical semiconductor device;
• forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter;
• and
• forming a second electrical contact to a second gate structure to a second of the first and second conductivity type vertically orientated semiconductor device providing the floating gate connection for the inverter.