Semiconductor logic device and system and method of embedded packaging of same
AssigneeGeneral Electric Company
InventorsRaymond Albert Fillion, Kaustubh Ravindra Nagarkar
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Abstract
A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.
Claims21
A reconfigured semiconductor logic device comprising:
- a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon;
- and
- a redistribution layer comprising:
- an insulating layer disposed on the active surface of the semiconductor logic device;
- and
- a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer, wherein the plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer, and wherein the plurality of discrete terminal pads are larger than the plurality of I/O pads;
- wherein the plurality of discrete terminal pads comprise:
- a plurality of signal terminal pads electrically coupled to signal I/O pads of the plurality of I/O pads;
- a plurality of power terminal pads electrically coupled to power I/O pads of the plurality of I/O pads;
- and
- a plurality of ground terminal pads electrically coupled to ground I/O pads of the plurality of I/O pads.
(canceled)
A method of manufacturing a reconfigured semiconductor logic device comprising:
- forming an insulating layer on an active surface of a semiconductor logic device;
- forming a plurality of vias through the insulating layer to expose a plurality of input/output (I/O) pads on the active surface;
- disposing a conductive material on a top surface of the insulating layer and into the plurality of vias;
- and
- patterning the conductive material to form a plurality of electrically isolated terminal pads electrically coupled to respective I/O pads of the plurality of I/O pads through the plurality of vias, the plurality of electrically isolated terminal pads larger than the respective I/O pads;
- wherein forming the plurality of electrically isolated terminal pads comprises:
- forming a first subset of the plurality of electrically isolated terminal pads to electrically couple to signal I/O pads of the plurality of I/O pads;
- and
- forming a second subset of the plurality of electrically isolated terminal pads to electrically couple to power and ground I/O pads of the plurality of I/O pads, the second subset of the plurality electrically isolated terminal pads larger than the first subset.
(canceled)
An electronics package comprising:
- a reconfigured semiconductor device comprising:
- a semiconductor device;
- and
- a reconfiguration layer comprising:
- an insulating layer covering an active surface of the semiconductor device having a plurality of input/output (I/O) pads located thereon;
- and
- a plurality of discrete terminal pads electrically coupled to the plurality of I/O pads through the insulating layer, the plurality of discrete terminal pads being larger than the plurality of I/O pads;
- and
- a multi-layer interconnect structure comprising:
- a first interconnect insulating layer formed atop the reconfiguration layer;
- and
- a first conductive wiring layer plated on a top surface of the first interconnect insulating layer, the first conductive wiring layer extending through a plurality of sets of parallel vias formed through the first interconnect insulating layer to contact the plurality of discrete terminal pads, wherein each set of parallel vias is aligned above a respective terminal pad of the plurality of discrete terminal pads.
21-28. (canceled)
Dependencies are inferred from the claim text.