Back to results
US 2019/0157226 A1Published application
Semiconductor logic device and system and method of embedded packaging of same
AssigneeGeneral Electric Company
InventorsRaymond Albert Fillion, Kaustubh Ravindra Nagarkar
Life of this patent
Estimating the term…
Abstract
A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.
Claims30
A reconfigured semiconductor device comprising:
- a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon;
- and
- at least one redistribution layer overlying the active surface of the semiconductor device, each at least one redistribution layer comprising:
- an insulating layer;
- and
- a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.
3 more elements
A method of manufacturing a reconfigured semiconductor device comprising:
- disposing an insulating layer over an active surface of a semiconductor logic device, the active surface comprising a plurality of input/output (I/O) pads arranged in a uniform grid at a non-solderable pitch;
- forming a plurality of vias through the insulating layer;
- disposing a layer of conductive material on an outer surface of the insulating layer, into the plurality of vias, and onto the plurality of I/O pads;
- and
- patterning the layer of conductive material to form a plurality of discrete terminal pads, each discrete terminal pad electrically coupled to a respective I/O pad of the plurality of I/O pads.
2 more elements
An embedded electronics package comprising:
- an insulating material;
- a reconfigured semiconductor device embedded within a cavity of the insulating material, the reconfigured semiconductor device comprising:
- a semiconductor device comprising a plurality of input/output (I/O) pads having a pitch less than a minimum pitch for solder bump attachment;
- and
- a redistribution layer comprising:
- a redistribution insulating layer disposed atop the semiconductor device;
- and
- a plurality of terminal connections each comprising a conductive pad formed on the redistribution insulating layer and a conductive via extending through the redistribution insulating layer to couple a respective conductive pad to a respective I/O pad of the plurality of I/O pads;
- and
- at least one interconnect layer overlying the reconfigured semiconductor device and a first surface of the insulating material, the at least one interconnect layer comprising:
- an interconnect insulating layer;
- and
- a conductive wiring layer formed on the interconnect insulating layer and extending into a plurality of vias therein to electrically couple with the plurality of terminal connections.
10 more elements
A method of manufacturing an embedded electronics package comprising:
- embedding a reconfigured semiconductor device within an insulating material, the reconfigured semiconductor device comprising a semiconductor device having a plurality of input/output (I/O) pads arranged in a uniform grid at a non-solderable pitch, an insulating layer disposed on the semiconductor device, and a plurality of discrete terminal pads formed on an outer surface of the insulating layer and electrically coupled to respective I/O pads of the plurality of I/O pads through the insulating layer;
- and
- forming an overlay interconnect structure atop the reconfigured semiconductor device and a first surface of the insulating material, the overlay interconnect structure comprising an overlay insulating layer and a patterned conductive wiring layer extending through the at least one overlay insulating layer to contact the plurality of discrete terminal pads of the reconfigured semiconductor device.
A semiconductor logic device comprising:
- a semiconductor base substrate;
- and
- an area array of input/output (I/O) pads formed on a surface of the semiconductor base substrate at a non-solderable pitch, the area array comprising a plurality of signal I/O pads, a plurality of power I/O pads, and a plurality of ground I/O pads.
An embedded electronics package comprising:
- an insulating material;
- a semiconductor logic device embedded within a cavity of the insulating material, the semiconductor logic device comprising:
- a semiconductor base substrate;
- and
- an area array of input/output (I/O) pads formed on a surface of the semiconductor base substrate at a non-solderable pitch, the area array comprising a plurality of signal I/O pads, a plurality of power I/O pads, and a plurality of ground I/O pads;
- and
- at least one interconnect layer overlying the semiconductor logic device and a first surface of the insulating material, the at least one interconnect layer comprising:
- an interconnect insulating layer;
- and
- a conductive wiring layer formed on the interconnect insulating layer and extending into a plurality of vias therein to electrically couple with the plurality of signal I/O pads, the plurality of power I/O pads, and the plurality of ground I/O pads.
7 more elements
Dependencies are inferred from the claim text.