Chip package and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChuei-Tang Wang, Chen-Hua Yu
Life of this patent
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Abstract
A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.
Claims20
A chip package, comprising:
- a redistribution layer;
- at least one first semiconductor chip and an integrated fan-out package, electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package comprises at least one second semiconductor chip;
- and
- an insulating encapsulation, encapsulating the at least one first semiconductor chip and the integrated fan-out package.
A chip package, comprising:
- a redistribution layer;
- at least one first semiconductor chip and an integrated fan-out package, electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package comprises:
- a redistribution circuit structure;
- at least one second semiconductor chip and at least third semiconductor chip, located on and electrically connected to the redistribution circuit structure;
- an encapsulant, encapsulating the at least one second semiconductor chip and the at least third semiconductor chip;
- and
- conductive features, located on and electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is located between the encapsulant and the conductive features;
- and
- an insulating encapsulation, encapsulating the at least one first semiconductor chip and the integrated fan-out package.
A manufacturing method of a chip package, comprising:
- providing a first carrier;
- disposing at least one first semiconductor chip and an integrated fan-out package on the first carrier, the integrated fan-out package comprising at least one second semiconductor chip;
- encapsulating the at least one first semiconductor chip and the integrated fan-out package in an insulating encapsulation;
- forming a redistribution layer on the insulating encapsulation, the redistribution layer being electrically connected to the at least one first semiconductor chip and the integrated fan-out package, wherein the at least one first semiconductor chip and the integrated fan-out package are arranged side-by-side and on a surface of the redistribution layer;
- disposing conductive elements on the redistribution layer, wherein the redistribution layer is located between the insulating encapsulation and the conductive elements;
- and
- debonding the first carrier.
Dependencies are inferred from the claim text.