US 2019/0157158 A1 · SIMPLE CONTACT OVER GATE ON ACTIVE AREA

Abstract

Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure. The plurality of contacts is further formed such that the plurality of contacts are positioned in at least a portion of the insulating material configured to be deposited over the upper surface of the conductive metal material.

Claims20

Dependent claims

A method for fabricating a semiconductor device, comprising:

forming a field effect transistor (FET) device on a semiconductor substrate, the FET device comprising a source/drain layer, a first insulator layer on the source/drain layer and a gate structure comprising a gate electrode layer, a gate capping layer, and a gate sidewall spacer;
etching at least a portion of the first insulator layer to provide an opening having an exposed top surface of the source/drain layer, wherein the etching of at least a portion of the first insulator layer is selective to the gate structure;
depositing a conductive metal material to completely fill the opening;
patterning an upper surface of the conductive metal material to a target width of the conductive metal material and recessing the upper surface of the conductive metal material down to a target depth in the conductive metal material to provide a recessed opening;
forming a planarized second insulator layer on a top surface of the gate structure and to completely fill the recessed opening;
and
forming a metal contact opening in the planarized second insulator layer to an upper portion of the recessed opening and to at least a portion of a top surface of the gate structure below the gate capping layer;
and
depositing an interconnect conductor to completely fill the metal contact opening to a top surface of the second insulator layer.

6 more elements

Dependencies are inferred from the claim text.

Simple contact over gate on active area

Life of this patent

Simple contact over gate on active area

Life of this patent

Abstract

Claims20