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US 2019/0157144 A1Published application
Semiconductor device and forming method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Han LEE, Shih-Kang FU, Meng-Pei LU, Shau-Lin SHUE
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Abstract
A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.
Claims22
A method, comprising:
- forming a first metal into a first trench in a dielectric layer;
- forming a second metal over the first metal;
- performing a thermal treatment to the second metal such that an average grain size of the second metal is increased;
- and
- performing a first chemical mechanical polish (CMP) process to the second metal after the performing the thermal treatment using the first metal as a CMP stop layer.
2 more elements
6-7. (canceled)
A method, comprising:
- forming a barrier layer in a first trench in a dielectric layer;
- forming a first metal having a first crystal orientation ratio over the barrier layer;
- performing a thermal treatment to the first metal to form a treated first metal, wherein the treated first metal has a second crystal orientation ratio different from the first crystal orientation ratio;
- and
- performing a first chemical mechanical polish (CMP) process to the treated first metal using the barrier layer as a CMP stop layer.
2 more elements
(canceled)
An interconnection structure, comprising:
- a dielectric layer over a semiconductor substrate;
- and
- a first metal embedded in the dielectric layer, wherein (002) crystal orientation of the first metal is greater than a (101) crystal orientation of the first metal.
Dependencies are inferred from the claim text.