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US 2019/0156906 A1Published application
Sample hold circuit
AssigneeRohm Co., Ltd.
InventorsNaohiro NOMURA, Takatoshi MANABE
Life of this patent
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Abstract
A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.
Claims14
A sample hold circuit, comprising:
- at least one capacitor;
- and
- at least one complementary metal-oxide semiconductor (CMOS) switch,
- wherein each of the at least one CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel, and
- a high level of a gate signal of the NMOS transistor is adjusted to a voltage level lower than a power supply voltage of a chip on which the CMOS switch is integrated.
2 more elements
A sample hold circuit, comprising:
- at least one capacitor;
- and
- at least one CMOS switch,
- wherein each of the at least one CMOS switch includes an NMOS transistor and a PMOS transistor connected in parallel, and
- a high level of a gate signal of the NMOS transistor is lower than a high level of a gate signal of the PMOS transistor.
2 more elements
A semiconductor device, comprising:
- a CMOS switch including an NMOS transistor and a PMOS transistor connected in parallel;
- and
- a gate voltage adjustment circuit structured to adjust a high level of a gate signal of the NMOS transistor to a voltage level lower than a power supply voltage of a chip on which the CMOS switch is integrated.
Dependencies are inferred from the claim text.