Post write erase conditioning
AssigneeWestern Digital Technologies, Inc.
InventorsMohan Vamsi DUNGA, Changyuan CHEN, Biswajit RAY
Life of this patent
Estimating the term…
Abstract
A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
Claims20
A method of conditioning charge trap memory, the method comprising:
- programming at least a portion of a block in a charge trap memory;
- identifying deeply erased cells from the at least the programmed portion of the block of the charge trap memory;
- and
- reprogramming the identified deeply erased cells.
A storage device comprising:
- a memory comprising one or more programmed blocks for data storage, wherein the memory comprises a dielectric layer for charge trapping;
- a controller coupled with the memory and configured to identify deeply erased cells from the one or more programmed blocks of the memory;
- and
- a recondition circuitry configured to reprogram the identified deeply erased cells.
A memory system comprising:
- means for identifying deeply erased cells from at least a programmed portion of a block in a charge trap memory;
- and
- means for reprogramming the identified deeply erased cells.
Dependencies are inferred from the claim text.