Programming nand flash with improved robustness against dummy wl disturbance

A memory comprising:

• a plurality of memory cells arranged in series in a semiconductor body;
• a first string select switch between a reference line and a first end of the plurality of memory cells, and a second string select switch between a bit line and a second end of the plurality of memory cells;
• first and second dummy memory cells arranged in series between the first string select switch and a first edge memory cell at the first end or between the second string select switch and a second edge memory cell at the second end, the first dummy memory cell being adjacent one of the first and second edge memory cells, the second dummy memory cell being adjacent one of the first and second string select switches;
• a channel line including channels for the memory cells in the plurality of memory cells and the first and second dummy memory cells;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells;
• and
• control circuitry coupled to the plurality of word lines and the first and second dummy memory cells adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by:
• applying a switching voltage to the first dummy memory cell, the switching voltage stepping up to a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level during a second time interval;
• and
• during a third time interval, applying a program voltage to the selected word line, while keeping the second voltage level on the first dummy memory cell.