Quantum circuit libraries for floating-point arithmetic

2) The method of 1), wherein the library includes multiple floating point adders thereby allowing a tradeoff between circuit parameters.

3) The method of 1), wherein a number computed by the selected reversible circuit description is split into m bits of mantissa, e bits of exponent, and 1 sign bit, and wherein m can be an arbitrary non-negative integer and wherein e can be an arbitrary non-negative integer that can be chosen independently of m.

4) The method of 3), wherein the addition operation is implemented by computing the difference in exponents using a reversible circuit followed by an aligning of the mantissas by the difference followed by adding the mantissas, followed by a reversible test for overflows, and if needed, followed by a shift of the exponent.

5) The method of 1), wherein the selected reversible circuit description is for floating point addition, and wherein the floating point addition is performed with respect to twos complement encoding.

6) The method of 1), wherein the selected reversible circuit description is for floating point multiplication, and wherein the multiplication is implemented by determining a result exponent by adding the factors exponents, followed by multiplying mantissas in an 2m bit register, followed by a test for overflows

7) The method of 6), wherein the method further comprises a renormalization of the result.

8) A system, comprising:

• a processing device;
• and
• one or more storage devices storing computer-implementable instructions, which when implemented by the processing device, automatically generate reversible circuits for floating point addition or multiplication operations from given classical circuit descriptions.

14) The system of 12), wherein the selecting is performed at run-time.

15) The system of 10), wherein the underlying physical quantum computing device has boundary constraints, including a total number of available qubits, a maximum number of available gates, and a maximum available circuit depth.

16) The system of 12), wherein the addition and multiplication operations are obtained from classical circuit language descriptions, then decomposed into logical netlists

17) The system of 16), where the netlist is further decomposed into lookup tables, and finally mapped into reversible networks.

18) The system of 17) where the decomposition of the lookup tables into reversible networks is done using optimized circuits for implementing multiply controlled NOT circuits.

19) The system of 18) where the multiply controlled NOT circuits are mapped into sequences of Toffoli gates using available resources, including available clean or dirty ancillas.

20) One or more storage devices storing computer-implementable instructions, which when implemented by a processing device, automatically generate reversible circuits for floating point addition or multiplication operations from given classical circuit descriptions.