Arithmetic processing device

An arithmetic processing device comprising:

• a first storage device including at least one first array having memory elements arranged in a first direction and a second direction intersecting with the first direction;
• a second storage device including at least one second array having memory elements arranged in the first direction;
• a third storage device including at least one third array having memory elements arranged in the first and second directions, the third array having a smaller number of memory elements arranged in the first direction than the memory elements of the first array, arranged in the first direction, and having a smaller number of memory elements arranged in the second direction than the memory elements of the first array, arranged in the second direction;
• and
• a first process layer, using data stored in the memory elements of the third array, to perform a convolution process to data stored in the memory elements of the first array, and to store a result of the convolution process in the memory elements of the second array.