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US 2019/0155785 A1Published application
Multi-core control system
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Lae PARK, Soo Hyun KIM, Young Tae LEE
Life of this patent
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Abstract
Provided are multi-core control systems. A multi-core control system includes multiple cores including a first core; and a process dependency recognizer configured to recognize a dependency between processes each executed in the respective cores, wherein if the first core waits for a first period of time to execute a first process, the first core recognizes a process on which the first process depends by the process dependency recognizer.
Claims21
A multi-core control system comprising:
- multiple cores, including a first core and a second core;
- and
- a process dependency recognizer unit configured to identify a dependency between a first process executed in the first core and a second process executed in the second core, the first process being dependent on the second process,
- wherein the multi-core control system is configured such that when the first core waits for a first length of time to execute the first process, the first core transmits to the process dependency recognizer unit a request to identify the second process, and
- wherein, in response to the request to identify the second process transmitted from the first core, the process dependency recognizer unit identifies the second process, and transmits to the first core information identifying the second process.
2 more elements
A multi-core control system comprising:
- a first core having a first processing speed;
- a second core having a second processing speed;
- and
- a scheduler unit configured to assign a first process to the first core and a second process to the second core, the first process depending on the second process,
- wherein the multi-core control system is configured such that:
- when the first core waits for a first length of time to execute the first process, the first core evaluates the first processing speed and second processing speed and determines if the first processing speed is greater than the second processing speed, and
- when the first core determines that the first processing speed is greater than the second processing speed, the first core requests the scheduler unit to reassign the second process to a third core that has a third processing speed greater than the second processing speed.
4 more elements
-27. (canceled)
A system-on-chip comprising:
- an interface configured to receive a task request from a host;
- a first core and a second core, each configured to execute the task request;
- and
- a scheduler unit configured to assign a first process to the first core and a second process to the second core, wherein the first process is associated with the requested task, and the second process is associated with the requested task and precedes the first process in a processing order,
- wherein the first core is configured to:
- determine if the first process depends on the second process, if the first core waits for a first period of time to execute the first process,
- determine if a first processing speed of the first core is greater than a second processing speed of the second core, if the first core determines that the first process depends on the second process, and
- request the scheduler unit to reassign the second process to a third core having a third processing speed greater than the second processing speed, if the first core determines that the first processing speed is greater than the second processing speed.
5 more elements
Dependencies are inferred from the claim text.