Packet tunneling for multi-node, multi-socket systems
AssigneeHewlett Packard Enterprise Development LP
InventorsFrank R. Dropps, Michael Anderson, Michael Malewicki
Life of this patent
Estimating the term…
Abstract
Multi-node, multi-socket computer systems and methods provide packet tunneling between processor nodes without going through a node controller link. On receiving a packet, the destination node identifier (NID) is examined, and if it is not same as the source socket, then the packet request address is examined. If it is determined that the packet is not for a remote connected socket, then the packet's destination NID and source socket NID are replaced along with recalculated data protection information. The modified packet is then sent to the destination socket over another processor interconnect path.
Claims15
A computer system comprising:
- a plurality of multi-processor nodes each comprising:
- a plurality of sockets each identified within the respective node by a unique node identifier (NID) and each comprising a processor and a memory connected by an interface;
- a plurality of processor interconnects directly connecting at least some of the sockets in the node each to another socket in the node;
- and
- at least one node controller comprising:
- a plurality of processor ports for connection to sockets via processor interconnects, each processor port having a NID;
- and
- a plurality of node controller link ports for connection to other node controllers via node controller links;
- wherein, for at least a first of the node controllers, at least two processor ports share a single NID used by connected sockets to address the node controller as a proxy for other sockets connected within the system.
A node controller chip comprising:
- a plurality of divisions, each division comprising:
- at least one socket interface chiplet for connection via a processor interconnect to one of a plurality of sockets each socket identified within its respective node by a unique node identifier (NID) and each comprising a processor and a memory connected by an interface;
- a plurality of local home and remote home chiplets configured to route and track request and response packets;
- a plurality of system interconnect interface chiplets for connection via node controller links to other node controller chips;
- wherein at least two of the socket interface chiplets have a common NID associated therewith and are directly connected within the node controller chip to tunnel packets between socket interface chiplets without the packets being routed through the local home, remote home, or system interconnect interface chiplets.
A method comprising:
- a node controller receiving a command packet addressed to a destination socket from a source socket in a multiprocessor computer system comprising multiple nodes each having multiple sockets, each socket comprising at least one computer processor and a memory, each socket connected to other sockets in its node via memory-coherent interconnects;
- based on determining by examination of a destination identifier (destination ID) in the command packet that the destination socket is not the source socket, and further based on determining by examination of a request address in the command packet that the destination socket is not a remote connected socket to which the node controller is not connected via one of a plurality of processor ports in the node controller:
- replacing the destination ID in the command packet;
- replacing a source identifier (source ID) in the command packet;
- recalculating and replacing data protection information in the command packet;
- and
- the node controller sending the command packet to the destination socket over a memory-coherent interconnect different from the one over which it was received.
Dependencies are inferred from the claim text.