Safe double buffering using dma safe linked lists
AssigneeInfineon Technologies AG
InventorsSimon Cottam, Patrice Woodward
Life of this patent
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AssigneeInfineon Technologies AG
InventorsSimon Cottam, Patrice Woodward
Estimating the term…
A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.
A method for transferring data from a peripheral to a first memory buffer and a second memory buffer, the first and second memory buffers being arranged in parallel with one another at an interface of the peripheral, the method comprising:
A method, comprising:
A method, comprising:
Dependencies are inferred from the claim text.