Sending data off-chip

A processor comprising:

• an arrangement of multiple tiles on the same chip, each tile comprising its own separate respective processing unit and memory including program memory and data memory, wherein separate portions of program code are arranged to run in parallel in different ones of the tiles;
• an on-chip interconnect arranged to enable the code run on the different tiles to communicate between tiles;
• and
• an external interconnect comprising a non-time-deterministic mechanism implemented in dedicated hardware logic for communicating data off-chip, whereby data is sent over the external interconnect in the form of packets, each packet having a header in which a destination address is present, and whereby communication of packets over the external interconnect is non-time-deterministic;
• wherein the external interconnect comprises an external exchange block configured to provide flow control and queuing of the packets;
• wherein one of the tiles is nominated by a compiler of the code to send an external exchange request message to the exchange block, the external exchange request message comprising one or more control packets indicating which of the tiles have data packets to send to a destination on another chip;
• and
• wherein the exchange block is configured to perform said flow control by:
• A) sending an exchange-on control packet to a first of the tiles indicated in the exchange request message as having data to send externally, to cause the first tile to start sending packets to their destinations via the external interconnect, being queued in a queue of the exchange block;
• and then B) once this tile has sent its last data packet, sending an exchange-off control packet to this tile to cause it to stop sending packets, and sending another exchange-on control packet to the next tile indicated in the exchange request message as having data packets to send.