Apparatuses and methods for transferring data from memory on a data path
AssigneeMicron Technology, Inc.
InventorHiromasa Noda
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
Claims20
A switching buffer circuit comprising:
- a first data bus having a first data bus segment and second data bus segment;
- a first switching buffer provided on the first data bus and configured to drive data from the first data bus segment of the first data bus to the second data bus segment of the first data bus in a first direction;
- a second data bus having a first data bus segment and a second data bus segment;
- and
- a second switching buffer provided on the second data bus and configured to drive data from the first data bus segment of the second data bus to the second data bus segment of the second data bus in a second direction opposite to the first direction.
A method comprising:
- at a first switching buffer, driving data from a first data bus segment of a first data bus to a second data bus segment of the first data bus in a first direction;
- and
- at a second switching buffer, driving data from a first data bus segment of a second data bus to a second data bus segment of the second data bus in a second direction opposite to the first direction.
An apparatus comprising:
- a first switching buffer circuit comprising:
- a first input data bus segment and a first output data bus segment, the first input data bus segment and the first output data bus segment are coupled to a first data bus;
- a first switching buffer configured to drive data on the first data bus from the first input data bus segment to the first output data bus segment in a first direction;
- a second input data bus segment and second output data bus segment, the second input data bus segment and the second output data bus segment are coupled to a second data bus;
- and
- a second switching buffer configured to drive data on the second data bus from the second input data bus segment to the second output data bus segment in a second direction opposite to the first direction;
- and
- a second switching buffer circuit comprising:
- a third input data bus segment and a third output data bus segment, the third input data bus segment and the third output data bus segment are coupled to the first data bus;
- a third switching buffer configured to drive the data on the first data bus from the third input data bus segment to the third output data bus segment in the first direction;
- a fourth input data bus segment and fourth output data bus segment, the fourth input data bus segment and the fourth output data bus segment are coupled to the second data bus;
- and
- a fourth switching buffer configured to drive the data on the second data bus from the fourth input data bus segment to the fourth output data bus segment in the second direction.
Dependencies are inferred from the claim text.