Memory address translation

Memory address translation apparatus comprising:

• page table access means for accessing page table data to retrieve translation data defining an address translation between a initial memory address in a initial memory address space, and a corresponding output memory address in an output address space;
• translation data buffer means for storing, for a subset of the initial address space, one or more instances of the translation data;
• and
• control means, responsive to an input initial memory address to be translated, for requesting retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, for initiating retrieval of translation data for the input initial memory address by the page table access circuitry.

A method comprising:

• accessing page table data to retrieve translation data defining an address translation between a initial memory address in a initial memory address space, and a corresponding output memory address in an output address space;
• storing, for a subset of the initial address space, one or more instances of the translation data in a translation data buffer;
• in response to an input initial memory address to be translated, requesting retrieval of translation data for the input initial memory address from the translation data buffer;
• and
• before completion of processing of the request for retrieval from the translation data buffer, initiating retrieval of translation data for the input initial memory address by the page table access circuitry.