Semiconductor device and cache memory control method for reducing power consumption
AssigneeRenesas Electronics Corporation
InventorNaoshi ISHIKAWA
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Abstract
An object of the present invention is to effectively reduce power consumption. A semiconductor device according to the present invention includes a first cache memory, a second cache memory whose power consumption is larger than that of the first cache memory, and a main memory whose power consumption is larger than that of the second cache memory. Capacity of each of the first and second cache memories is determined so that a total value of values obtained by adjusting current values of the first cache memory, the second cache memory, and the main memory in accordance with hit ratios of the memories becomes a predetermine current threshold or less.
Claims13
A semiconductor device comprising:
- a first cache memory;
- a second cache memory whose power consumption is larger than that of the first cache memory;
- and
- a main memory whose power consumption is larger than that of the second cache memory,
- wherein capacity of each of the first and second cache memories is determined so that a total value of values obtained by adjusting current values of the first cache memory, the second cache memory, and the main memory in accordance with hit ratios of the memories becomes a predetermine current threshold or less.
A cache memory control method comprising:
- a determination step, when a data read request is generated from the high-order device, of determining whether a hit occurs in a first cache memory or not;
- and
- a stopping step, when occurrence of a hit in the first cache memory is determined, of stopping at least a part of operation of a second cache memory at a level lower than the first cache memory.
Dependencies are inferred from the claim text.