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US 2019/0155738 A1Published application
Scalable Coherent Apparatus and Method
AssigneeIntegrated Device Technology, Inc.
InventorMohammad Shahanshah Akhter
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Abstract
Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system.
Claims9
A scalable coherent communications method comprising:
- using a first directory cache coherent directory implemented within an on-chip cache coherent fabric to track coherency between on-chip cores;
- and
- using a second directory cache coherent directory implemented within an on-chip module to keep track of participating on-chip cores.
A system on a chip (SoC) apparatus comprising:
- an on-chip cache coherent interconnect connected to a plurality of cores, the on-chip cache coherent interconnect maintaining an on-chip cache coherency directory, maintaining transaction ordering for all on-chip cache coherent participating cores from the plurality of cores;
- and
- an external interface block connected to the on-chip cache coherent interconnect;
- wherein the external interface block maintains a scale-out cache coherency directory, maintains transaction order and flow control information, and handles off-chip RapidIO transaction processing.
1 more element
Dependencies are inferred from the claim text.