Soft chip-kill recovery for multiple wordlines failure
AssigneeSK hynix Inc.
InventorsNaveen Kumar, Aman Bhatia, Chenrong Xiong, Yu Cai, Fan Zhang
Life of this patent
Estimating the term…
Abstract
Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.
Claims20
A method implemented on a computer system to output data from superblocks of a memory that comprises a plurality of memory dies, the method comprising:
- decoding, in a decoding iteration, codewords from a superblock of the memory, wherein the superblock comprises a first block on a first memory die, a second block on a second memory die, and a third block on a third memory die, wherein the first block stores a first codeword of the codewords, wherein the second block stores a second codeword of the codewords, and wherein the third block stores XOR parity bits for the codewords;
- determining that the decoding of at least the first codeword and the second codeword failed in the decoding iteration based on a first number of error bits associated with the first codeword and on a second number of error bits associated with the second codeword, wherein the decoding of the first codeword in the decoding iteration is based on first soft information associated with the first codeword, and wherein the decoding of the second codeword in the decoding iteration is based on second soft information associated with the second codeword;
- selecting to decode, in a next decoding iteration, the first codeword prior to decoding the second codeword in the next decoding iteration based on the first number of error bits and the second number of error bits;
- generating, based on the first codeword being selected, updated first soft information associated with the first codeword, wherein the updated first soft information is generated by updating the first soft information based on the second soft information and the XOR parity bits;
- and
- decoding, in the next decoding iteration, the first codeword based on the updated first soft information.
A computer system comprising:
- a processor;
- and
- a memory comprising computer-readable instructions that, upon execution by the processor, cause the computer system to:
- decode, in a decoding iteration, codewords from a superblock, wherein the superblock comprises a first block on a first memory die, a second block on a second memory die, and a third block on a third memory die, wherein the first block stores a first codeword of the codewords, wherein the second block stores a second codeword of the codewords, and wherein the third block stores XOR parity bits for the codewords;
- determine that the decoding of at least the first codeword and the second codeword failed in the decoding iteration based on a first number of error bits associated with the first codeword and on a second number of error bits associated with the second codeword, wherein the decoding of the first codeword in the decoding iteration is based on first soft information associated with the first codeword, and wherein the decoding of the second codeword in the decoding iteration is based on second soft information associated with the second codeword;
- select to decode, in a next decoding iteration, the first codeword prior to decoding the second codeword in the next decoding iteration based on the first number of error bits and the second number of error bits;
- generate, based on the first codeword being selected, updated first soft information associated with the first codeword, wherein the updated first soft information is generated by updating the first soft information based on the second soft information and the XOR parity bits;
- and
- decode, in the next decoding iteration, the first codeword based on the updated first soft information.
One or more non-transitory computer storage media comprising instructions that, upon execution on a computer system, configure the computer system to perform operations comprising:
- decoding, in a decoding iteration, codewords from a superblock, wherein the superblock comprises a first block on a first memory die, a second block on a second memory die, and a third block on a third memory die, wherein the first block stores a first codeword of the codewords, wherein the second block stores a second codeword of the codewords, and wherein the third block stores XOR parity bits for the codewords;
- determining that the decoding of at least the first codeword and the second codeword failed in the decoding iteration based on a first number of error bits associated with the first codeword and on a second number of error bits associated with the second codeword, wherein the decoding of the first codeword in the decoding iteration is based on first soft information associated with the first codeword, and wherein the decoding of the second codeword in the decoding iteration is based on second soft information associated with the second codeword;
- selecting to decode, in a next decoding iteration, the first codeword prior to decoding the second codeword in the next decoding iteration based on the first number of error bits and the second number of error bits;
- generating, based on the first codeword being selected, updated first soft information associated with the first codeword, wherein the updated first soft information is generated by updating the first soft information based on the second soft information and the XOR parity bits;
- and
- decoding, in the next decoding iteration, the first codeword based on the updated first soft information.
Dependencies are inferred from the claim text.