Soft chip-kill recovery using concatenated codes
AssigneeSK hynix Inc.
InventorsNaveen Kumar, Aman Bhatia, Fan Zhang
Life of this patent
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Abstract
Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when writing data to a superblock of the memory, a wordline of the superblock stores “D+P” parity bits that protect “D” data bits of a codeword having a length of “2D+P.” Other wordlines of the superblock store codewords each having a length of “D+P” (e.g., “D” data bits and “P” parity bits). If the decoding of any of these codewords of length “D+P” fails, the “D+P” parity bits are used to re-decode the failed wordline.
Claims20
A method implemented on a computer system to output data from superblocks of a memory, the method comprising:
- generating “D” intermediary data bits by at least performing one or more XOR operations on data bits from wordlines of a superblock, wherein:
- the wordlines comprise a first wordline and a second wordline,
- the superblock comprises a first block on a first memory die and a second block on a second memory die,
- the first block comprises the first wordline and the second block comprises the second wordline, and
- each of the first wordline and the second wordline is configured to store “D” data bits and “P” parity bits,
- generating “K” parity bits that protect the “D” intermediary data bits, wherein “K” is equal to the sum of “D” and “P”;
- storing the “K” parity bits in an additional wordline of the superblock other than the wordlines;
- and
- outputting decoded data bits from the superblock based on a decoding procedure that uses the “K” parity bits stored in the additional wordline.
A computer system comprising:
- one or more processors;
- and
- one or more memories communicatively coupled with the one or more processors and storing instructions that, upon execution by the one or more processors, configure the computer system to at least:
- generate “D” intermediary data bits by at least performing one or more XOR operations on data bits from wordlines of a superblock, wherein:
- the wordlines comprise a first wordline and a second wordline,
- the superblock comprises a first block on a first memory die and a second block on a second memory die,
- the first block comprises the first wordline and the second block comprises the second wordline, and
- each of the first wordline and the second wordline is configured to store “D” data bits and “P” parity bits;
- generate “K” parity bits that protect the “D” intermediary data bits, wherein “K” is equal to the sum of “D” and “P”;
- store the “K” parity bits in an additional wordline of the superblock other than the wordlines;
- and
- output decoded data bits from the superblock based on a decoding procedure that uses the “K” parity bits stored in the additional wordline.
One or more non-transitory computer storage media comprising instructions that, upon execution on a computer system, configure the computer system to perform operations comprising:
- generating “D” intermediary data bits by at least performing one or more XOR operations on data bits from wordlines of a superblock, wherein:
- the wordlines comprise a first wordline and a second wordline,
- the superblock comprises a first block on a first memory die and a second block on a second memory die,
- the first block comprises the first wordline and the second block comprises the second wordline, and
- each of the first wordline and the second wordline is configured to store “D” data bits and “P” parity bits;
- generating “K” parity bits that protect the “D” intermediary data bits, wherein “K” is equal to the sum of “D” and “P”;
- storing the “K” parity bits in an additional wordline of the superblock other than the wordlines;
- and
- outputting decoded data bits from the superblock based on a decoding procedure that uses the “K” parity bits stored in the additional wordline.
Dependencies are inferred from the claim text.