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AssigneeInternational Business Machines Corporation
InventorsLakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
Estimating the term…
Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
A system comprising:
The system of claim 6, further comprising movement of the operating system from a first hardware system to a second hardware system wherein a third table on a second hardware system is changed to include the entity identifier associated with a second window context.
A computer program product for memory translation fault resolution between a processing core and a hardware accelerator, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by a processor to:
A method for memory translation fault resolution between a processing core and a hardware accelerator, the method comprising:
Dependencies are inferred from the claim text.